1. Field of the Invention
The present invention relates to multiplex switching networks, and more particularly to a programmable analog multiplex switching network with a charge-coupled-device switching means.
2. Background Art
U.S. Pat. No. 3,740,480 issued Jun. 19, 1973 to Krupp et al. entitled TIME DIVISION MULTIPLEX SWITCHING SYSTEM UTILIZING ALL TIME DIVISION TECHNIQUES discloses time slot interchangers in each of plural input time division multiplex signal paths to a switching network shift input time slot signals to respective operational time slots corresponding to different switching circuits. A mass serial-parallel converter takes all of the input path signals from the mentioned interchangers in each time slot and steers them in series to switching circuit corresponding to that operational time slot. Further, time slot interchangers shift the signals in the respective switching circuits to new time slot positions corresponding to different output circuits. Another converter steers the new time slot signals from all of the switching circuits in series to the output circuit corresponding to that new time slot. Finally, time slot interchangers in each of the output circuits to destination time slot positions thereby completing both the line switching and the time slot interchanging operations.
U.S. Pat. No. 3,740,480 is distinct from the present invention in that it describes a switching system and merely mentions charge coupled device (CCD) technology without describing how this switching system can be realized in CCD architecture. The schematic and circuit diagram describe digital, e.g. CMOS implementation of the switching circuit. No mention of analog signal switching network or method of realization is included.
U.S. Pat. No. 4,154,986, issued May 15, 1979 to Howells et al. entitled TIME SLOT INTERCHANGE NETWORK describes a time slot interchanging network for use in digital switching. Two shift registers are used, one coupled to receive information from the incoming highway, the other coupled to feed information to the outgoing highway. The shift registers are identical in bit capacity and coupled in parallel. A circulating memory operative at the clock rate of the registers is synchronized with the incoming register to control transfer gates feeding the outgoing register.
U.S. Pat. No. 4,154,986 is distinct from the present invention in that it covers digital sort/sequence network where each pixel in a charge coupled device (CCD) implementation stores a 1 or 0 state of a bit; not analog video/or Analog Telephony signals. It describes selective transfer between two CCD registers using timed transfer gate control pulses.
U.S. Pat. No. 4,399,458 issued Aug. 16, 1983 to Berry et al. entitled SIGNAL PROCESSING SYSTEM relates to a signal processing system having an analogue shift register of the charge coupled type fed from a sampling device and controlled by a clock arrangement having three independent clocks. One clock determines the sampling rate of sampling device and the rate at which such samples are clocked into register. Another clock determines the rate at which stored samples are clocked out of the register. The two clocks operate in the MHz range. The third clock operates in the KHz range and dictates the sample storage interval and clocks the stored samples through a number of storage sites in register during the storage interval to reduce the adverse effects of geometrical and other inhomogeneities of the individual register sites on the individual stored samples.
U.S. Pat. No. 4,399,458 is distinct from the present invention in that it only relates to charge coupled device delay time. U.S. Pat. No. 4,628,347 issued Dec. 9, 1986 to Sato et al. entitled CHARGE TRANSFER DEVICE FOR MULTIPLEXING SIGNALS relates to a charge transfer device for multiplexing signals and eliminates an output circuit and level adjusting circuit necessary for multiplexing signals in the prior art. There are provided at least two first and second transfer channels and for transferring signal charges and a third transfer channel for alternately multiplexing the signal charges which are transferred within the first and second transfer channels. To the first and second transfer channels is supplied the same transfer clock signal and to the third transfer channel is supplied a second transfer clock signal with a frequency of which is n times the transfer channels before the signals are multiplexed, a multiphase clock with different phases of the clock being applied to spatially corresponding electrodes is used in the invention. The invention can be used as a signal multiplexing charge transfer device for a color solid state image sensor which uses an image sensing element such as CCD.
U.S. Pat. No. 4,628,347 Sato et al is distinct from the present invention in that it shows 2:1 MUX by selecting one of two charge input channels and switching in onto an output channel. It does not discuss a time multiplex concept applied to the switching MUX, and does not discuss the case of multiple outputs, as well as inputs. It does not discuss issues of parallel loading stored signal thru several parallel bridges.